During formation of replacement gates for NFETs and PFETs, first one area (e.g., the PFET) is masked off over a nitride cap to define the second area (e.g., the NFET), and a portion of the nitride cap over the second area is removed. Then the second area is masked off over the remaining nitride cap of the second area to define the first area. In the process, a portion of the nitride cap for the first area is removed. Where the masks used to define the NFET and PFET areas overlap, a nitride bump is formed. For example, as illustrated in FIG. 1A, polysilicon gates 101 (or dummy gates 101) are formed with nitride caps 103 between spacers 105 on a silicon substrate 107 with shallow trench isolation (STI) regions 109 formed therein. Nitride caps 103 may be formed, for example of silicon nitride (SiN). A TJ mask 111 is formed over the PFET regions with openings to define the NFET regions, and a portion of the nitride caps 103 is etched away. Then, as illustrated in FIG. 1B, the TJ mask 111 is removed, and an RG mask 113 is formed over the NFET regions with openings to define the PFET regions. Again a portion of the nitride caps 103 is etched away, leaving nitride bumps 115. Adverting to FIG. 1C, RG mask 113 is removed, and a premetal dielectric (PMD) 117 of an oxide, for example silicon oxide (SiO), is deposited over the entire substrate. A first chemical mechanical polishing (CMP) is performed down to the nitride bumps 115, and a second CMP and buff are performed to remove the nitride bumps, as illustrated in FIG. 1D. Then the remaining nitride of the nitride caps 103 is removed by reactive ion etching (RIE) or remote plasma nitride etch to reveal the polysilicon gates 101 for forming the replacement gates.
The size of the nitride bumps depends on the amount of TJ/RG mask overlap and, therefore, varies. In addition, a higher etch amount occurs at the edges of the TJ and RG masks, resulting in a large variation in nitride cap thickness after PFET/NFET definition, as shown in FIG. 1F. Use of the CMP buff to remove the nitride bumps will cause large dishing in the iso/wide STI regions. Also, a large overetch is needed during the nitride RIE or remote plasma nitride etch to ensure complete nitride removal and successful opening of the polysilicon gates.
A need therefore exists for methodology enabling improved control of non-uniformity etch rate and gate height, and the resulting device.